;**** includes **** 
.include "2313def.inc"
; Output immediate   outi	port,var
.macro	outi
	ldi	r16,@1
	out	@0,r16
.endm
;*****************************
.def	temp1	= r16
.def	temp2	= r17
.def	temp3	= r18
.def	c1		= r19
.def	time	= r20
.def	time_w	= r21
.def	tc	= r22
.def	c	= r23
.def	d1	= r24
.def	d2	= r25
.def	d3	= r26
.def	d4	= r27

;**  PORTB  ***
.equ	jp1	=0
.equ	jp2	=1
.equ	jp3	=2
;		=3
;		=4
;		=5
;		=6
;		=7
;**  PORTD  **
.equ	test	=0
;		=1
;		=2
;		=3
;		=4
;		=5
.equ	cr	=6
;*********************
.cseg 
	rjmp	 start			 ;各種ﾘｾｯﾄ
	reti; 	 RJMP	EXT_INT0	 ;外部割り込み要求0
	reti; 	 RJMP	EXT_INT1	 ;外部割り込み要求1
	reti;	 RJMP	TIM_CAPT1	 ;ﾀｲﾏ/ｶｳﾝﾀ1 捕獲(ｷｬﾌﾟﾁｬ)発生
	rjmp	 	TIM_COMP1	 ;ﾀｲﾏ/ｶｳﾝﾀ1 比較一致
	reti; 	 RJMP	TIM_OVF1	 ;ﾀｲﾏ/ｶｳﾝﾀ1 ｵｰﾊﾞｰﾌﾛｰ
	reti; 	 RJMP	TIM_OVF0	 ;ﾀｲﾏ/ｶｳﾝﾀ0 ｵｰﾊﾞｰﾌﾛｰ
	reti; 	 RJMP	UART_RXC	 ;UART受信完了
	reti; 	 RJMP	UART_DRE	 ;UART送信ﾊﾞｯﾌｧ空
	reti; 	 RJMP	UART_TXC	 ;UART送信完了
	reti; 	 RJMP	ANA_COMP	 ;ｱﾅﾛｸﾞ比較器出力遷移
;*********************
start:
	ldi	 R16,LOW(RAMEND)	;RAM最終ｱﾄﾞﾚｽ下位を取得
	out	 SPL,R16	 		;ｽﾀｯｸ ﾎﾟｲﾝﾀ下位を初期化
	ldi	temp1,0
	out	DDRB,temp1	; pb0~7 in port
	ldi	temp1,0xff	; pb0~7 pull up
	out	PORTB,temp1		
	ldi	temp1,0x41
	out	DDRD,temp1	; pd1~5 in port ,0/6out port
	ldi	temp1,0x3e	; pd1~5 pull up	
	out	PORTD,temp1	; pd0/6 clear

	ldi	temp1,200
	rcall	wait_ms
t_set:
	in	temp1,PINB
	andi 	temp1,0x07	;pb2~0 get
	cpi	temp1,0x07	;jp 000
	brne	t_set0
	ldi	time,4
	rjmp	timer1_set	
t_set0:
	cpi	temp1,0x06	;jp 001
	brne	t_set1
	ldi	time,8
	rjmp	main	
t_set1:
	cpi	temp1,0x05	;jp 010
	brne	t_set2
	ldi	time,12
	rjmp	timer1_set		
t_set2:
	cpi	temp1,0x04	;jp 011
	brne	t_set3
	ldi	time,20
	rjmp	timer1_set
t_set3:
	cpi	temp1,0x03	;jp 100
	brne	t_set4
	ldi	time,40
	rjmp	timer1_set
t_set4:
	cpi	temp1,0x02	;jp 101
	brne	t_set5
	ldi	time,80
	rjmp	timer1_set
t_set5:
	cpi	temp1,0x01	;jp 110
	brne	t_set6
	ldi	time,120
	rjmp	timer1_set
t_set6:
	ldi	time,240	;jp 111

timer1_set:
	outi	TIMSK,1<<OCIE1A			;タイマ１比較A一致割込み許可
	outi	TCCR1B,(1<<CTC1)|(1<<CS11)	;タイマ１比較A一致後クリア、TCK=CK/8
	outi	OCR1AH,high(37500)		;割込み周期　75ms
	outi	OCR1AL, low(37500)		;75ms/(1/500k)=37,500
	outi	TCNT1H,0
	outi	TCNT1L,0
	sei
	ldi	tc,200		;50ms*200=15s
	mov	time_w,time
main:
	nop
	rjmp	main

TIM_COMP1:
	sbis	PIND,test
	rjmp	TIM_COMP1_1
	cbi	PORTD,test
	rjmp	TIM_COMP1_2
TIM_COMP1_1:
	sbi	PORTD,test
TIM_COMP1_2:
	dec	tc
	brne	TIM_COMP1_e
	ldi	tc,200		
	dec	time_w
	brne	TIM_COMP1_e
	mov	time_w,time
	rcall	sousin	
TIM_COMP1_e:
	reti


sousin:
	ldi	d1,0x7f
	ldi	d2,0x80
	ldi	d3,0xdc
	ldi	d4,0x61
sbit:
	ldi	c,255
pulse_s:
	ldi	temp1,8
	sbi	PORTD,cr
	rcall	wait_us
	ldi	temp1,17
	cbi	PORTD,cr
	rcall	wait_us

	dec	c
	brne	pulse_s
sbit1:
	ldi	c,87
pulse_s1:
	ldi	temp1,8
	sbi	PORTD,cr
	rcall	wait_us
	ldi	temp1,17
	cbi	PORTD,cr
	rcall	wait_us
	dec	c
	brne	pulse_s1
		
	ldi	temp1,45
	rcall	wait_100us

data:
	ldi	c1,0
data1:
	lsl	d1
	rol	d2
	rol	d3
	rol	d4
	brcs	iti
zero:	
	rcall crm
	ldi	temp1,56
	rcall	wait_10us
	rjmp	data2
iti:
	rcall crm
	ldi	temp1,168
	rcall	wait_10us
data2:	
	inc	c1
	cpi	c1,32
	brne	data1
stopbit:
	rcall crm
exit:
	ret
	

crm:
	ldi	c,21
crm1:
	ldi	temp1,8
	sbi	PORTD,cr
	rcall	wait_us
	ldi	temp1,17
	cbi	PORTD,cr
	rcall	wait_us
	dec	c
	brne	crm1
	ret



;base 4MHz	
wait_us:
	nop			; 1clocks
	dec	temp1		; 1clocks
	brne	wait_us		; 2clocks
	ret

wait_10us:
	;temp1x10us  40clocks
	
	ldi	temp2,9
	
wait_10us1:
	nop			; 1clocks
	dec	temp2		; 1clocks
	brne	wait_10us1	; 2clocks

	nop			; 1clocks
	dec	temp1		; 1clocks	
	brne	wait_10us	; 2clocks
	ret

wait_100us:	;temp1x100us  400clocks

	ldi	temp2,99		
wait_us_01:
	nop			; 1clocks
	dec	temp2		; 1clocks
	brne	wait_us_01	; 2clocks

	nop			; 1clocks
	dec	temp1		; 1clocks	
	brne	wait_100us	; 2clocks
	ret
wait_ms:
				;temp1　ms
	ldi	temp2,125

wait_ms_01:
	ldi	temp3,7
wait_ms_02:
	nop			; 1clocks
	dec	temp3		; 1clocks
	brne	wait_ms_02	; 2clocks

	nop			; 1clocks
	dec	temp2		; 1clocks
	brne	wait_ms_01	; 2clocks

	dec	temp1		; 1clocks	
	brne	wait_ms		; 2clocks
	ret
